Synthesis of robust delay-fault-testable circuits: theory

Correct operation of synchronous digital circuits requires propagation delays of all sensitizable paths in the circuit to be smaller than a speciied limit. Physical defects and processing variations in integrated circuits can aaect the temporal behavior of a circuit without altering the logical behavior. These defects are called delay faults. In order to design, and especially to synthesize, highly or completely delay-fault testable circuits, one has to fully understand the sources of untestability. Ideally this requires the determination of necessary and suucient conditions for delay-fault testability. Synthesis procedures that produce testable logic realizations by satisfying suucient conditions for delay-fault testability can then be based on this understanding. There is often an area/performance overhead associated with these procedures, but an understanding of both the suuciency conditions and the techniques of logic optimization can alleviate the overhead by minimally constraining the optimization to achieve full testability. In this paper we give a comprehensive theoretical framework for the analysis and synthesis of delay-fault testable combinationallogic circuits. In particular, we provide necessary and suucient conditions for a combinational logic network to be completely robustly path-delay-fault testable. We begin with two-level circuits and give a necessary and suucient condition for robust path-delay-fault testability in terms of the well known concepts of primality, irredundancy and essential vertices. We then apply these notions to multilevel circuits to arrive at a necessary and suucient condition for multilevel implementations. We also generalize these results to multiple-output functions. We show that algebraic factorization retains the robust path-delay-fault testability of a two-level circuit and this naturally suggests a synthesis procedure for multilevel robustly path-delay-fault testable circuits. We switch focus to a less restrictive though common model of delay faults, namely, gate-delay-faults. We give a necessary and suucient condition for two-level and multilevel functions to be completely robustly gate-delay-fault testable. We show that constrained algebraic factorization in a multilevel synthesis procedure retains the complete robust gate-delay-fault testability of a two-level network. We present preliminary experimental results using these synthesis techniques.